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# Voltage Amplification Help (page 2)

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By McGraw-Hill Professional
Updated on Sep 11, 2011

## Voltage Amplification Practice Problem

#### Problem

Examine Fig. 16-12. Note that the curves in the graph become farther apart as the drain voltage E D increases (that is, as we move toward the right). Extrapolating on this graph, it is apparent that if E D exceeds a certain level, the curves become horizontal lines, and they no longer spread out any farther. What can we infer about the ability of this JFET to amplify signals as its E D increases indefinitely?

Fig. 16-12 . A family of characteristic curves for a hypothetical n -channel JFET.

#### Solution

When a JFET is operated at relatively low drain voltages, a certain pk-pk gate signal voltage (say, from −2 to −1 V) produces a small change in drain current I D . As E D increases, the curves represented by gate voltages E G = −2 V and E G = −1 V grow farther apart; this means that the same input signal will result in larger changes in I D . This translates into more amplification. As E D continues to increase, the curves represented by E G = −2 V and E G = −1 V level off, and their separation becomes constant. The amplification factor does not increase significantly once E D exceeds this limiting value. This is illustrated in Fig. 16-13. This same thing will happen for all ac signals with relatively small pk-pk voltages that fall within the ranges indicated by the curves. Of course, there is a limit to all this. If E D becomes too large, the device will be physically damaged. Most JFETs are designed for operation with E D values of no more than a few tens of volts.

Fig. 16-13 . Illustration for the above problem.

Practice problems of these concepts can be found at: Semiconductors Quiz

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