Voltage Amplification Help (page 2)
The graph in Fig. 16-11 shows the drain (channel) current, I D as a function of the gate bias voltage E G for a hypothetical n -channel JFET when no signal is applied to the gate electrode. The drain voltage E D is assumed to be constant.
Fig. 16-11 . Relative drain current as a function of gate voltage in a hypothetical n -channel JFET.
When E G is fairly large and negative, the JFET is pinched off, and no current flows through the channel. As E G gets less negative, the channel opens up, and current begins flowing. As E G gets still less negative, the channel gets wider, and the current I D increases. As E G approaches the point where the source-gate ( S-G ) junction is at forward breakover, the channel conducts as well as it possibly can. If E G becomes positive enough so that the S-G junction conducts, the JFET no longer works properly. Some of the current in the channel is shunted through the gate. This is like a garden hose springing a leak.
The best amplification for weak signals is obtained when E G is such that the slope of the curve in Fig. 16-11 is steepest. This is shown roughly by the range marked X in the graph. For power amplification, results are often best when the JFET is biased at or beyond pinchoff, in the range marked Y .
Drain Current Versus Drain Voltage
Drain current I D can be plotted as a function of drain voltage E D for various values of gate bias voltage E G . The resulting set of curves is called a family of characteristic curves for the device. Figure 16-12 shows a family of characteristic curves for a hypothetical n -channel JFET. Also of importance is the curve of I D versus E G , one example of which is shown in Fig. 16-11.
Look back for a moment at the discussion of dynamic current amplification for bipolar transistors earlier in this chapter. The JFET analog of this is called dynamic mutual conductance or transconductance .
Refer to Fig. 16-11. Suppose that E G is a certain value, with a corresponding I D that flows as a result. If the gate voltage changes by a small amount Δ E G , then the drain current also will change by a certain increment Δ I D . The transconductance is the ratio Δ I D /Δ E G . Geometrically, this translates to the slope of a line tangent to the curve of Fig. 16-11 at some point.
The value of Δ I D /Δ E G is not the same everywhere along the curve. When the JFET is biased beyond pinchoff, as in the region marked Y in Fig. 16-11, the slope of the curve is zero. There is no drain current, even if the gate voltage changes. Only when the channel conducts some current will there be a change in I D when there is a change in E G . The region where the transconductance is the greatest is the region marked X , where the slope of the curve is steepest. This is where the most amplification can be obtained. A small change in E G produces a large change in I D , which in turn causes a large variation in a resistive load placed in series with the line connecting the drain to the power supply.
Voltage Amplification Practice Problem
Examine Fig. 16-12. Note that the curves in the graph become farther apart as the drain voltage E D increases (that is, as we move toward the right). Extrapolating on this graph, it is apparent that if E D exceeds a certain level, the curves become horizontal lines, and they no longer spread out any farther. What can we infer about the ability of this JFET to amplify signals as its E D increases indefinitely?
Fig. 16-12 . A family of characteristic curves for a hypothetical n -channel JFET.
When a JFET is operated at relatively low drain voltages, a certain pk-pk gate signal voltage (say, from −2 to −1 V) produces a small change in drain current I D . As E D increases, the curves represented by gate voltages E G = −2 V and E G = −1 V grow farther apart; this means that the same input signal will result in larger changes in I D . This translates into more amplification. As E D continues to increase, the curves represented by E G = −2 V and E G = −1 V level off, and their separation becomes constant. The amplification factor does not increase significantly once E D exceeds this limiting value. This is illustrated in Fig. 16-13. This same thing will happen for all ac signals with relatively small pk-pk voltages that fall within the ranges indicated by the curves. Of course, there is a limit to all this. If E D becomes too large, the device will be physically damaged. Most JFETs are designed for operation with E D values of no more than a few tens of volts.
Fig. 16-13 . Illustration for the above problem.
Practice problems of these concepts can be found at: Semiconductors Quiz
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